This site is an independent educational reference on thin-film metrology and semiconductor process technology. Our focus is on explaining the principles and trade-offs of deposition methods, including the distinction between chemical vapor deposition (CVD) and physical vapor deposition (PVD).
The technical content here draws on preserved historical documentation from a former metrology systems group based in Natick, Massachusetts. That group developed non-contact optical measurement technologies, including SurfaceWave laser-based systems and model-based infrared reflectometry, for monitoring interconnect layers in advanced copper and low-k processes on 200mm and 300mm wafers.
We present this material for its engineering and educational value, not as a claim of current commercial activity. No ongoing company, product availability, or certification is implied. The archived descriptions of process control and measurement challenges remain useful for understanding how CVD and PVD approaches are evaluated in real fabrication environments.
Thin film deposition is one of the most fundamental unit processes in semiconductor fabrication. The two dominant families of deposition techniques are Chemical Vapor Deposition (CVD) and Physical Vapor Deposition (PVD). While both produce solid films on a wafer, they achieve this through fundamentally different physics and chemistry. Understanding these differences is critical for process engineers because the choice between CVD and PVD determines not only the film's properties but also the thermal budget of the device, the conformality over topography, and the integration scheme for the entire flow.
The core distinction lies in how the film forms. In PVD, the material that ends up on the wafer is physically transported from a solid or liquid source. The source material is vaporized—typically by sputtering (ion bombardment) or evaporation (thermal heating)—and the vapor travels in a line-of-sight path to the wafer, where it condenses. There is no chemical change; the film is the same composition as the target, though stoichiometry can be adjusted by adding reactive gases (reactive sputtering) like nitrogen or oxygen to form nitrides or oxides.
In CVD, the film is synthesized on the wafer surface through a chemical reaction. Gaseous precursors are introduced into a chamber, and they react either in the gas phase or, more commonly, on the heated wafer surface. The reaction produces a solid film and volatile byproducts that are pumped away. The key point is that the film material is not present in the source; it is created from the molecular building blocks of the precursors. This chemical pathway allows for a much wider range of film compositions, including complex alloys and doped films, that are difficult or impossible to make by simple physical condensation.
Temperature is a primary differentiator. PVD processes, especially sputtering, can be run at relatively low wafer temperatures, often near room temperature or only slightly elevated. This is because the energy for film formation comes from the kinetic energy of the sputtered atoms, not from thermal activation of a chemical reaction. Evaporation is also a low-temperature process for the wafer, though the source is hot. This low thermal budget makes PVD attractive for back-end-of-line (BEOL) metallization, where the underlying dielectric and transistor structures cannot tolerate high temperatures.
CVD, by contrast, generally requires elevated temperatures to drive the chemical reaction. The exact temperature depends on the precursor chemistry and the activation energy of the reaction. Some CVD processes, like low-pressure CVD (LPCVD) for silicon nitride, run at high temperatures. Others, like plasma-enhanced CVD (PECVD), use a plasma to provide energy to the precursors, allowing the wafer to stay at a lower temperature. However, even PECVD typically runs hotter than most PVD sputtering processes. The thermal budget is a major constraint: if the underlying device has already been formed with dopant profiles or silicide contacts, a high-temperature CVD step can cause unwanted diffusion or degradation. Therefore, the choice often comes down to whether the film can be deposited at a temperature compatible with the existing layers.
Step coverage—the ability to coat vertical sidewalls and bottom corners of trenches and vias uniformly—is where the two techniques diverge most dramatically. PVD is inherently line-of-sight. Atoms travel in straight lines from the target to the wafer. On a flat surface, this is fine. But on a topography with high-aspect-ratio features, the sidewalls are shadowed, and the bottom of deep trenches receives little or no deposition. This results in poor step coverage, with thin or discontinuous films on vertical surfaces and a tendency to form overhangs at the top corners of features. For this reason, PVD is generally chosen for blanket films on planar surfaces or for layers where conformality is not critical, such as the seed layer for electroplating, where a thin, continuous film on the bottom and sidewalls is sufficient because the subsequent plating fills the feature.
CVD, on the other hand, is driven by surface reactions. Precursor molecules adsorb onto all surfaces—top, bottom, and sidewalls—and react there. In an ideal surface-reaction-limited regime, the deposition rate is uniform across the entire topography, yielding excellent conformality. This makes CVD the preferred choice for filling high-aspect-ratio structures like shallow trench isolation (STI), interlayer dielectrics, and contact liners. However, not all CVD is perfectly conformal. If the reaction is mass-transport-limited (i.e., the precursor is consumed faster than it can diffuse into a deep trench), the bottom of the feature will receive less precursor, leading to poor fill. Process engineers tune pressure, temperature, and precursor flow to operate in the surface-reaction-limited regime for good step coverage. Advanced techniques like atomic layer deposition (ALD), a variant of CVD, achieve perfect conformality by alternating precursor pulses, but ALD is slow and used only for critical thin layers.
PVD films, particularly sputtered metals, tend to be very dense and have low impurity levels because there is no chemical byproduct to incorporate. However, sputtered films often have high compressive stress due to the energetic bombardment of the depositing atoms. This stress can be tuned by adjusting the sputtering pressure and bias, but it is a constant concern for film adhesion and wafer bow.
CVD films can have higher impurity levels, such as hydrogen or carbon, depending on the precursor chemistry. For example, PECVD silicon nitride contains significant hydrogen, which affects its etch rate and dielectric constant. However, CVD offers better control over film stress through process parameters like RF power and gas ratios. For dielectric films, CVD is often preferred because it can produce films with lower intrinsic stress and better gap-fill properties.
In practice, the selection follows a clear logic based on the film's role.
For metal interconnects and barrier/seed layers, PVD is the workhorse. Sputtered titanium, tantalum, and their nitrides are used as adhesion layers and diffusion barriers at the bottom of vias and contacts. The poor sidewall coverage is acceptable because the barrier only needs to be thick enough at the bottom to prevent diffusion, and the subsequent copper seed layer is also deposited by PVD. The low temperature of PVD is essential here, as these steps occur after the transistors are formed.
For dielectric layers that must fill gaps or coat complex topography, CVD is chosen. STI oxide fill, interlayer dielectrics (ILD), and passivation layers are all deposited by CVD, often using PECVD or high-density plasma CVD (HDP-CVD) to achieve good gap-fill at moderate temperatures. The conformality of CVD ensures that the dielectric uniformly coats the sidewalls of metal lines, providing electrical isolation without voids.
For silicon and silicon-germanium epitaxy, CVD is the only viable option because the film must be a single crystal that extends the crystal lattice of the underlying substrate. PVD cannot achieve epitaxial growth. This is used in source/drain engineering and for channel strain.
For thin, highly conformal films like gate dielectrics or high-k layers, ALD (a CVD variant) is chosen, not PVD, because only ALD can provide atomic-level thickness control and perfect conformality on 3D structures like FinFETs.
In summary, the rule of thumb is: use PVD when you need a dense, low-temperature metal film on a relatively planar surface or as a seed/barrier; use CVD when you need conformal coverage, gap-fill, or a film whose composition requires a chemical reaction. The thermal budget of the device and the aspect ratio of the features are the two deciding factors that dominate the engineering tradeoff.
This independent educational reference summarizes general technical concepts. Verify current standards, dimensions, and manufacturer specifications before making a procurement or engineering decision.